IMPLEMENT FULL ADDER USING NAND GATES AS TWO LEVELS REALISATIONS.

 

Half & Full Adder | Half & Full Subtractor – AHIRLABS

Aim: Implement full adder using NAND gates as two level realizations.

Apparatus Required: -

Digital Trainer kit, single strand wires, breadboard, NAND (IC-7400).

Theory :

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full-adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from the previous less-significant stage. The full adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit output. Output carry and sum typically represented by the signals Cout and S, where the sum equals 2Cout + S.

One example implementation is with

S = A B Cin

and

Cout = (A B) + (Cin (A B)).

The truth table for the full adder is:

Inputs

Outputs

A

B

Cin

Cout

S

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

 

Full Adder using NAND gates only:-


As mentioned earlier, a NAND gate is one of the universal gates and can be used to implement any logic design. The circuit of full adder using only NAND gates is shown below.

PROCEDURE:

I.            Place the breadboard gently on the observation table.

II.          Fix the IC which is under observation between the half shadow line of breadboard, so there is no shortage of voltage.

III.       Connect the wire to the main voltage source (Vcc) whose other end is connected to last pin of the IC .

IV.        Connect the ground of IC to the ground terminal provided on the digital lab kit.

V.          Connect output pins to the led on digital lab kit.

VI.        Switch on the power supply.

 BY: HARDEEP KUMAR

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