Aim: (a) Use of 4-bit shift register for shift left and shift right operations.
(b) Use4-bit
shift register as a ring counter.
APPARATUS REQUIRED: -
Logic trainer kit, D Flip-flop IC - 7474 wires.
THEORY:
Serial In/Shift Right/Serial Out Operation
Data is shifted in the right hand direction one bit at a time with each transition of the clock signal. The data enters the shift register serially from the left hand side and after four clock transitions the 4-bit registers has 4-bbits of data. The data is shifted out serially one bit at a time from the right hand side of the register if clock signals are continuously applied. Thus after 8 clock signals the 4-bit data is completely shifted out of the shift register.
Serial In/Serial Right/Serial Out Operation
Serial shift registers can be implemented using any type of flip-flops. A serial shift register implemented using D flip-flops with the serial data applied at the D input of the first flip-flop and serial data out obtained at the Q output of the last flip-flop is shown in figure. At each clock transition 1 bit of serial data is shifted in and at the same instant 1-bit of serial data is shifted out. For a 4-bit shift register, 8 clock transitions are required to shift in 4-bit data and completely shift out the 4-bit data. As the data shifted out 1-bit at a time, a logic 0 value is usually shifted in to fill up the vacant bits in the shift register.
Serial In/Shift Right/Serial Out Register
Timing diagram of a Serial In/Shift Right/Serial Out Register
Ring Counter
A ring counter is a special type of application of the Serial IN Serial OUT Shift register. The only difference between the shift register and the ring counter is that the last flip flop outcome is taken as the output in the shift register. But in the ring counter, this outcome is passed to the first flip flop as an input. All of the remaining things in the ring counter are the same as the shift register.
In the Ring counter
Below is the block diagram of the 4-bit ring counter. Here, we use 4 D flip flops. The same clock pulse is passed to the clock input of all the flip flops as a synchronous counter. The Overriding input(ORI) is used to design this circuit.
The Overriding input is used as clear and pre-set.
Working
The ORI input is passed to the PR input of the first flip flop, i.e., FF-0, and it is also passed to the clear input of the remaining three flip flops, i.e., FF-1, FF-2, and FF-3. The pre-set input set to 0 for the first flip flop. So, the output of the first flip flop is one, and the outputs of the remaining flip flops are 0. The output of the first flip flop is used to form the ring in the ring counter and referred to as Pre-set 1.
In the above table, the highlighted 1's are pre-set 1.
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the Shift register was designed and their truth table is verified.
PRECATIONS:
· All connections should be made neat and tight.
· Digital lab kits and ICs should be handled with utmost care.
· While making connections main voltage should be kept switched off.
· Never touch live and naked wires.
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